Source: Mentor Blog
Posted May 23, 2018
On May 15, Mentor, a Siemens Business, held its annual Silicon Valley User2User (U2U) conference at the Santa Clara Marriott.
Two keynotes by Dr. Wally Rhines, president and CEO of Mentor and Hooman Moshar, vice-president of engineering at Broadcom, opened the event.
The keynote from Dr. Wally Rhines was titled “Semiconductor Specialization Drives New Industry Structure.” The presentation drove home the idea that the semiconductor industry is neither consolidating nor de-consolidating. It is instead specializing.
Hooman Moshar’s keynote was titled “Power, the Nemesis,” made clear that today low power is the most critical design criteria for chips at 14nm and below.
The keynotes were followed by user presentations grouped into nine tracks: Calibre, AMS Verification, Veloce Emulation Platform, Questa Functional Verification, Xpedition High-Density Advanced Packaging, HLS & RTL/GL Low Power, Ultra Low-Power/ Ultra High-Density Memory IP, Tanner EDA: MEMS and Custom/Analog Design for the IoT Era, and Tessent Silicon Test Solutions.
I shared the stage with Neil Hand, director of marketing for the IC Verification Solutions division to open the Veloce and Questa tracks. Our shared presentation titled “A Roadmap to the Digital Twin with Verification and Validation,” highlighted many of the new technology areas the divisions are working on.
For the emulation track, four users took the stage in sequence.
Afzal Malik, verification manager at Cisco, discussed an approach to maximize emulation value for networking designs. Mentioning six verification challenges in networking designs, Afzal stated that emulation is a must have in the verification arsenal thanks to five main criteria: acceleration factor vs simulation, performance independent of designs size, full design debug, straightforward compilation and execution, reuse of verification components between simulation and emulation. Combining simulation and emulation, Cisco can achieve 100% coverage before tape-out. Moving on to the Veloce platform, Afzal listed the uses of Veloce from pre-silicon software development, to multi-chip verification, silicon bringup and readiness, and pre-silicon power analysis, providing a short description of the capabilities for each. The presentation then focused on the Veloce’s Ethernet Packet Generator and Monitor (EPGM), a virtual networking tester, its features and benefits. In summary, Afzal shared some performance metrics. In chip initialization, Veloce reached 200X speedup over simulation out-of-the-box, and 2,000X after optimization by parallelizing the test sequences, only possible in emulation. In packet streaming, Veloce achieved 15,000X acceleration over simulation.
In the next session, Tariq Masood, AMD Fellow, described multi-level modeling techniques for pre-silicon software development and design verification. After introducing AMD’s SimNow™ tool, a virtual platform for pre-silicon design verification, Tariq spoke to key features, components, deployment modes and benefits, Tariq then discussed the challenges and opportunities for pre-silicon shift-left validation. By combining SimNow with emulation, he described several hybrid configurations and concluded by listing the benefits obtainable by adopting the hybrid platform:
· Hybrid models running graphics workloads 8-10 weeks before SoC
· Significantly broad real-world stimulus can be run in pre-silicon
· Same front-end and/or stimulus used across virtual platforms, emulation, and silicon
· With efficiency gains, more teams are able to use emulators and for longer durations
· AMD Infinity Fabric simplified hybrid building blocks; building new configurations is much easier
· Comprehensive power and performance testing is now possible much earlier
In summary, Tariq concluded that embracing IP-level hybrid emulation was a game changer for AMD.
Sridhar Sundaram, Principal Engineer, power and thermal architecture lead at Samsung Austin Research Center (SARC), presented the next session. Sridhar discussed an integrated hybrid environment for power analysis by enumerating the key power challenges in today’s state-of-the-art designs. These include detecting high power and low efficiency phases of workload early in the design cycle, project power-constrained and thermal-constrained performance of key workloads, tuning of all of the above early in the design cycle across a broad range of benchmarks and end-user (Android) applications. He then proceeded to describe a peak power snippet flow built around Veloce. Sridhar showed several charts comparing emulated data from the Veloce Power App “power plot” versus silicon data, showing the consistency and correlation between the two. Sridhar concluded with an illustration of a hybrid platform that allows for switching from virtual models to emulated models to analyze specific areas of interest for power consumption.
Speaking for Bruce Cheng, chief ASIC architect at Starblaze, Ben Whitehead, product solutions specialists at Mentor, discussed how Starblaze combines ASIC simulation with Veloce emulation to accelerate the firmware design schedule for their SSD controllers. First, Ben acknowledged the Starblaze team for implementing an SSD system from concept to delivery in less than two years, a feat hard to achieve. He then went on to explain that critical to the success was the ability to start developing the firmware, the key component in a state-of-the-art SSD controller, at essentially the same time as hardware design. Ben then described a unified simulator/emulator environment based on the Veloce platform that enables early testing of the hardware/firmware integration, including hardware and software verification and system validation. This environment gives Starblaze the ability to find and fix bugs in hours.
In conclusion, the 2018 U2U conference was another success in the history of the Mentor emulation division (MED). Customers networked, interacted among themselves and with MED attendees and exchanged interesting experiences. This annual event is well worth putting on your calendar for next year.