“Have it your way” seems like just the right strategy to get a chip design verified correctly
Source: EETimes
In May 2014, Burger King announced it was scrapping its 40-year-old slogan, “Have it your way.” I say, let’s make it our own to describe the hardware emulation space, where the tools are having a remarkable impact on taming the verification challenges facing system-on-chip designers.
It wasn’t all that long ago when hardware emulation was hardly mentioned as a practical solution to these challenges. If it were to be mentioned, the remarks may have included an eye roll or a shoulder shrug. Oh, sure, verification engineers could be seen making their way to a far-off back room to use a clunky, big-box emulator nested in the middle of a dreadful convolution of long and unreliable cables to debug a graphics chip or microprocessor.
Those were the days when emulators were hard to use, required a full-time on-site specialist, and came with a fire extinguisher because of their tendency to overheat (regularly). The software support was rather rudimentary — especially when compared to modern offerings — and mainly limited to the compilation of the register transfer level (RTL) code into the emulation box. They were also single-user resources that were expensive to purchase and even more so to maintain. It wasn’t unusual for their cost to exceed the entire budget allocated to the verification task of a new design. Few project teams could justify one in their budget.
All that has changed in the past few years. Verification toolboxes today include a variety of choices for verification groups, and priority is given to emulation systems, which are now mandatory.
Hardware emulators are used now to clean a large design of all residual bugs uncovered by RTL simulation and formal analysis before silicon availability. As a design debugger, they must be efficient, which means easy to use, effective, and fast.
The move to emulation is being driven by increasing hardware design complexity and the fact that there is much more embedded software in each design. Consequently, the hardware emulation market, owned by three large vendors, is expanding rapidly — revenue is about $350 million now, and Gary Smith EDA forecasts that number will hit $1 billion by 2017 (subscription required).
Modern emulators are powered by custom ASIC-based or FPGA-based designs that present tradeoffs in their features and capabilities. These days, a visitor to an engineering department could see an emulation box sitting under a desktop or a datacenter chock full of large, high-capacity emulators that look nothing like the big-box emulators of yore. This is good news for verification engineers, who now enjoy far more options.
Regardless of the implementation, all modern emulators are multi-user resources. They come in different shapes, sizes, and footprints, depending on power consumption needs, and they offer enough capacity to accommodate most designs. Only at the upper end — more than 1 billion ASIC gates — do physical dimensions and power consumption tax the “processor-based emulator.”
Custom ASIC-based emulators are more flexible and offer advantages over commercial FPGA-based emulators. For one thing, the time-to-emulation factor for custom ASIC-based emulators is much faster than it is with commercial FPGA-based ones. To further expand the choices, a verification manager can select from two rather distinct classes of custom ASIC-based emulators. In one class, the processing element is a custom FPGA that is designed for emulation applications and would be a rather poor choice for a general-purpose FPGA. In fact, Mentor Graphics, which supplies such a system, calls it a custom emulator-on-chip. In the second class, the processing element consists of a vast array of rather simple Boolean processors that father the “processor-based emulator.” Cadence’s Palladium is implemented with such technology.
Custom ASIC-based emulators excel in debugging capabilities, ensuring 100% design visibility without requiring compilation and avoiding a significant drop in performance.
As for the commercial FPGA-based emulator, it has a smaller footprint, is lighter, and consumes less power than its counterparts. This type of emulator is fairly reliable and can handle up to 3 billion ASIC-equivalent gates. Though it’s a “Have it your way” market today, it’s still caveat emptor (or “buyer beware”) — the time to emulation isn’t nearly as fast as it is for other emulation solutions, and that needs careful evaluation.
Today, software support is a world apart from the old days. Most of the features and capabilities found in the treasured HDL simulator can be found in modern emulators, from assertions support to power analysis. Some offer functional coverage analysis, as well. They can still be deployed in an in-circuit emulation mode, but the transaction-based acceleration mode is the new favorite. In this mode, an emulator can interface to a test environment described at a high level of abstraction, typically in the SystemVerilog language, rendering the emulator remote accessible and opening the door to the datacenter as a hosted global resource.
With the growing variety and usage models of hardware emulation, wouldn’t you agree that relegating that oft-repeated Burger King slogan to the pile of trite old chestnuts would be a mistake? “Have it your way” seems like just the right strategy to get a chip design verified correctly.
— Lauro Rizzatti is a management consultant. He was formerly general manager and vice president of marketing of EVE-USA before Synopsys acquired it in 2012. Previously, he held positions in management, product marketing, technical marketing, and engineering. He can be reached at lauro@rizzatti.com.