Source: Verification Horizons There are intrinsic limitations in the current approach for estimating dynamic power consumption. Briefly, the approach consists of a file-based flow that evolves through two steps. First, a simulator or emulator tracks the switching activity either cumulatively for the entire run in a switching activity interchange format (SAIF) file, or on a cycle-by-cycle … Read more
Source: Verification Horizons THE SECOND DECADE In the second decade, the hardware emulation landscape changed considerably with a few mergers and acquisitions and new players entering the market. The hardware emulators improved notably via new architectures based on custom ASICs. The supporting software improved remarkably and new modes of deployment were devised. The customer base … Read more
By switching to an emulation-based methodology, a company developing application processor units (APUs) can bring up the design on the emulator in days, and typical design changes can be accommodated in less than a day. Source: Electronic Design This year’s International Computer Electronics Show (CES) continued to amaze me with a never-ending display of mindboggling electronic … Read more
The unstoppable rise in design sizes has been taxing heavily the EDA verification tools. Dynamic power estimation tools are one example. Source: EE Times Several incentives entice consumers to upgrade their mobile gadgets frequently. From more functionality and enhanced user experience, to a more attractive user interface to enliven usage, lighter weight, longer battery life, and … Read more
By eliminating a file-based flow, new tools offer a complete RTL power exploration and accurate gate-level power analysis process. Source: EE Times In a recent post, I highlighted the intrinsic limitations of the current approach to estimate dynamic power consumption. Briefly, the approach consists of a file-based flow that evolves through two steps. First, a simulator … Read more
Source: EDACafe Emulation is enjoying its moment in the spotlight and none too soon. Design complexity of all types has conspired to make chip verification an arduous task. These days, the fabric of system-on-chip (SoC) designs includes several processing cores, large sets of specialized IP, a plethora of peripherals and complex memories, routinely pushing the design … Read more
Source: Tech Design Forum The Design Automation Conference (DAC) program is now available at www.dac.com. It offers something for just about all chip designers and embedded software developers. I have just one gripe. While functional verification plays a significant role in panels, paper sessions and tutorials, I couldn’t find a standalone session on hardware emulation, the foundation … Read more
Is it time for the industry to devise a nimbler, faster and more efficient methodology? Source: Semiconductor Engineering If you wonder how important low power is in chip design today, consider the recent news in the blogosphere reporting the controversy surrounding Qualcomm’s Snapdragon 810 SoC — the company’s first flagship 64-bit chip, which will most likely … Read more
The OS shields the software from the hardware and assures the compatibility of any new and old software with any new or old hardware platform For more than a decade, I have been following the practice of upgrading my laptop every three years. I do so for more than one reason. After three years of … Read more
Design capacity in hardware emulators, also the compilation flow, is heavily dependent on the type of technology used in the verification engine. Source: EETimes In my last blog post, I described differences in the maximum design capacity of a software simulator versus that of a hardware emulator, highlighting that not all emulators are created equal. In … Read more