https://semiwiki.com/eda/siemens-eda/308264-scalable-verification-solutions-at-siemens-eda/ Siemens EDA Lauro Rizzatti recently interviewed Andy Meier, product manager in the Scalable Verification Solutions Division at Siemens EDA. Andy is a product manager in the Scalable Verification Solutions Division at Siemens EDA. Andy has held positions in the electronics and high-tech fields during his 20-year career including: Sr. Product Marketing manager at Siemens EDA, Product … Read more

https://www.eeweb.com/behind-the-scenes-expanding-the-siemens-ic-verification-portfolio-with-veloce-profpga/ Siemens acquired the proFPGA product family from Pro Design in 2021. I recently spoke with Gunnar Scholl, former CEO of Pro Design and now director of engineering in the Scalable Verification Solution Division (SVSD) at Siemens, and Gabriele Pulini, product marketing manager in SVSD at Siemens. Gunnar, what was the motivation to sell proFPGA? … Read more

https://semiwiki.com/eda/siemens-eda/306602-from-now-to-2025-changes-in-store-for-hardware-assisted-verification/ Siemens EDA Lauro Rizzatti recently interviewed Jean-Marie Brunet, vice president of product management and product engineering in the Scalable Verification Solution division at Siemens EDA, about why hardware-assisted verification is a must have for today’s semiconductor designs. A condensed version of their discussion is below. LR: There were a number of hardware-assisted verification announcements in 2021. … Read more

https://verificationacademy.com/verification-horizons/september-2021-volume-17-issue-2/veloce-hardware-assisted-verification-complete-unified-and-progressive Despite abundant rumors predicting the end of life for Moore’s Law (the axiom stating transistor density doubles every 24 months), semiconductor design sizes continue to grow exponentially with no end in sight. In the process, design sizes push costs off the roof. According to market research International Business Strategies (IBS), the total cost of … Read more

https://www.eeweb.com/whats-behind-hardware-emulations-rising-status/ Five common questions often come up when chip designers and verification engineers ask me about hardware emulation. All are well-considered and answers are widely shared. Today, emulation is mandatory in the design verification toolbox. Why? For two unrelated reasons: the ever-increasing demand for performance and throughput from verification tools and the remarkable progress in … Read more

https://bit.ly/3qEnywg In the span of a few short months earlier this year, Mentor Graphics became Siemens EDA and introduced a suite of integrated hardware-assisted verification tools, the first product launch under the new Siemens EDA brand. Jean-Marie Brunet, senior director of marketing, product management and product engineering at Siemens EDA, orchestrated the launch and connected … Read more

In summary: Emulators provide the capacity and debug visibility needed for verifying large SoCs, including hardware, software drivers, operating systems, and portions of application code. Enterprise FPGA prototypes provide higher-performance hardware for running emulation regression suites, executing ICE tests, and verifying application software. Desktop FPGA prototypes are available to software developers who want more direct contact with their … Read more

https://bit.ly/2TlNz7g Editor’s note: Two years ago, Lauro Rizzatti talked with Thomas Delaye, product engineering director at Siemens EDA, about applying machine learning to hardware emulation. (See: Can AI Help Manage the Data Needed for SoC Verification?) Rizzatti recently asked Delaye for an update. What follows is a condensed version of their conversation. Lauro Rizzatti: Fast forward, … Read more

A quick glance in today’s design verification toolbox reveals a variety of point tools supporting the latest system-on-chip (SoC) design development. When combined and reinforced by effective verification methodologies, these tools trace even the most hard-to-find bug, whether in software or in hardware. The focus on tools and delivering a tightly woven integration between complementary … Read more

If chip design had a face, it would have a wrinkle or two, an especially deep one caused by the increasingly complex challenge of hardware and software verification. Until recently, these two elements of a system design were done separately and at different times, with hardware design often beginning way ahead of software development. Generic … Read more