With AI/ML chip designs containing between 5 billion and 10 billion gates, design verification using hardware emulation is the answer, although not all hardware emulators are the same Artificial intelligence/machine learning (AI/ML) is the ultimate hot topic of 2019, taking hold of chip design and the semiconductor industry’s imagination and not letting go — for … Read more
In a recent talk on deep learning, BabbleLabs CEO Chris Rowen said, “I think of it as the construction of a complex numerical model that mimics the behavior of an even more complex but hidden system. The hidden system in question is often the brain.” Source: ElectronicDesign Lauro Rizzatti | Feb 06, 2019 Deep learning is one … Read more
Silicon system design with deep learning has the same challenges with other complex system-on-chip-based designs, only more so Source: EEWeb By Lauro Rizzatti (Contributed Content) | Tuesday, January 22, 2019 In a recent presentation to a group of semiconductor industry executives, Chris Rowen, CEO and co-founder of BabbleLabs, stated that there are two important ways to look at … Read more
Changes to 2020 SSD controllers versus 2018 SSD controllers are comparable to the task of migrating from HDD controllers to SSD controllers Source: EEWeb By Lauro Rizzatti (Contributed Content) | Thursday, December 20, 2018 In the technology sector, occasionally a new requirement will drive a minor technical concern into a big issue. If not addressed properly and in … Read more
Combining these Apps with an emulation environment makes it possible to increase fault coverage, increase production yield, and reduce ATE test time and cost Source: ElectronicDesign Lauro Rizzatti | Dec 19, 2018 The design-for-test (DFT) technology was driven by the need to harness the runaway cost of testing silicon chips on the manufacturing floor. This phenomenon eventually … Read more
Mipsology’s Zebra Deep Learning inference engine is designed to be fast, painless, and adaptable, outclassing CPU, GPU, and ASIC competitors Source: EEWEB By Lauro Rizzatti (Contributed Content) | Friday, November 23, 2018 I recently attended the 2018 Xilinx Development Forum (XDF) in Silicon Valley. While at this forum, I was introduced to a company called Mipsology, a startup in … Read more
A more efficient flow to support DSP development groups, such as VSORA’s, could help to ensure the success of 5G Source: EEWEB By Lauro Rizzatti (Contributed Content) | Tuesday, November 06, 2018 VSORA, a startup from Paris, recently emerged from stealth mode with a new approach to accelerate 5G broadband design. Khaled Maalej, its founder and CEO, and … Read more
Source: EDN Network Lauro Rizzatti -October 24, 2018 There are challenges unique to designing ASICs for networking applications. One is that bandwidth and latency performance tests for these devices require significantly more simulation cycles than required by other types of ICs. Of course the extended simulation slows the entire design process. To address these and other issues, … Read more
Reading the transcriptions and watching the videos of these three talks delivers an exhilarating look at the semiconductor industry’s future Source: EEWEB By Lauro Rizzatti (Contributed Content) Friday, September 21, 2018 Reading the transcriptions and watching the videos of these three talks delivers an exhilarating look at the semiconductor industry’s future Technical conferences and other industry events offer … Read more
Source: TECH DESIGN FORUM By Lauro Rizzatti September 20, 2018 This case study describes how the Beijing-based start-up realized its T10 Plus SSD controller using a simultaneous flow. Starblaze is a Beijing-based fabless start-up. It was established in 2015, and taped out the prototype of its first target design, an SSD controller, within six months. Starblaze went … Read more