Lauro Rizzatti The 2016 Mentor Graphics’ User Group boasted five technical sessions focused on emulation Source: EETimes The 2016 Mentor Graphics’ User Group, or U2U, was held at the Marriott Santa Clara on April 26. According to the opening remarks by Don Kurelich, Americas technical director at Mentor Graphics, it was attended by about 900 visitors. I had … Read more
Enhancing data center network security and packet transmission features has contributed to a rising gate count for networking SoCs, but even in the face of growing complexity, market windows can’t be missed Source: EECatalog In the contest for the most complex and largest chips on the market today, the mighty networking chip shares the crown with … Read more
Source: EDACafé Of course, anyone who reads my blog posts on EDACafe knows I have a huge bias toward hardware emulation –– In fact, my blog is called Hardware Emulation Journal! I’ve been a part of this Design Automation market segment since 1995 and continue to believe it is the most versatile of all verification tools. … Read more
Source: EDACafé What happens when a project team under a tight schedule takes delivery on a tool promised to change the way it does chip design and verification and it doesn’t live up to the promise? Why, the vendor sends in a village of AEs, R&D engineers and PhDs, of course, to work onsite with the … Read more
Source: EDACafé Many proponents and users of hardware emulation continue to enthuse about its benefits, expanding use models and growing popularity among hardware design and verification engineering groups. We believe it is the foundation of almost all verification strategies today, not replacing simulation, but augmenting it. The topic of hardware emulation’s popularity is starting to show … Read more
Source: Evaluation Engineering Design for testability (DFT), a way to build testability into an integrated circuit (IC) at the design stage to lower testing costs and increase manufacturing yield, has been around for many years in several different forms. These methodologies—ad-hoc and structured—are able to effectively detect all faults in a circuit, reducing cost and time … Read more
Hardware emulation is widely considered the universal verification tool that can be used throughout the SoC development cycle Source: Electronic Design The Design Automation Conference — that veritable shopping bazaar for design automation tools — is fast approaching, and verification teams are starting to make their “must see” lists of vendors. Chief among them has to … Read more
Source: ChipDesign Several years ago, while at Automatic Test Equipment (ATE) leader Teradyne, I witnessed frequent debates on a fundamental dilemma: On the production/testing floor, is it better to pass a failing device or reject a good device? Obviously, both are bad choices. If you reject a good device, you shoot yourself in the foot since … Read more
Source: EDACafé The folks at DVCon have done a brilliant thing. They’ve invited Lauro Rizzatti to present at their upcoming conference on a topic that Rizzatti knows better than anybody, emulation. Last year alone, he wrote 40 articles on the subject. More importantly, of course, Rizzatti helped guide EVE, the high-flying European EDA company that led the field in emulation from their base in … Read more
Marrying high-performance hardware with “smart” applications will make emulators workhorses for addressing complex system-level design verification challenges Source: EETimes DVCon, a conference for design and verification engineers, kicks off next week in San Jose, California. At this conference, hardware emulation will be a much-discussed topic in the program and in hallway conversations. After three decades of … Read more